The present invention relates to a semiconductor device having an insulated gate, and particularly to a semiconductor device having a structure for high-speed operation and excellent breakdown strength.
Recently, power MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have come to be used in large quantities as power switching devices with high breakdown strength, which can operate at high frequencies. For example, such power switching devices are disclosed in U.S. Pat. No. 4,532,534 and Fuji Jiho, Vol. 61, No. 11, pp. 697-700. FIG. 5 shows a schematic diagram, as viewed from the surface, newly drawn for explaining these devices conceptually. In a power MOSFET or IGBT 1, first insulated gate electrodes 4 are formed in stripes on a semiconductor substrate 1, and these first insulated gate electrodes 4 are electrically connected to a second insulated gate electrode 6 surrounding the first insulated gate electrodes 4. Reference numeral 10 indicates an electrode wire supplying control power to the insulated gate electrodes 4, 6.
FIG. 6 shows a cross-sectional structure taken along the line VI--VI of FIG. 5.
In FIG. 6, the semiconductor substrate 1 has a couple of main surfaces 101, 102, and has a n.sup.+ or p.sup.+ substrate region 11 of high impurity concentration formed adjacent one main surface 101, an n.sup.- layer 12 of low impurity concentration formed adjacent the substrate region 11, and a plurality of p-type layers 113 of higher impurity concentration than that of the n.sup.- layer 12 formed geometrically separated from one another in the n.sup.- layer 12. In each p-type layer 113, there are formed separately two n.sup.+ layers 114 of higher impurity concentration than that of the p-type layer 113. In a unit cell region of the semiconductor device, the p-type layer 113 is contiguous to a p.sup.+ layer 115 which has a well deeper than that of the p-type layer 113. At the other main surface 102, an n.sup.- layer 12, the p-type layers 113, and the n.sup.+ layers are exposed. A collector electrode 2 is in ohmic contact with the surface of the substrate region 11, while at the other main surface 102, an emitter electrode 3 is in ohmic contact with two n.sup.+ layers 114, the p-type layers 113 located between the two n.sup.+ layers 114, and p.sup.+ layers 115. First insulated gate electrodes 4 are formed, with interposition of an insulating film 5, such that they extend from above the n.sup.- layer 12, over and beyond the p-type layers 113, to the n.sup.+ layers 114. In the peripheral area of the semiconductor device, the p-type layer 113 is contiguous to the p.sup.+ layer 115 located closer to the periphery and having a well deeper than that of the p.sup.+ layer 115. A second insulated gate electrode 6 is formed on the p.sup.+ layer with interposition of a thick insulating film 7. The emitter electrode 3 is insulated from the first and second gate electrodes 4, 6 by an insulating film 8.
As described above, a power MOSFET or an IGBT is divided into the region A where a unit cell centering around the first insulated gate electrode 4 is formed repeatedly and the peripheral region B other than the region A.
To turn on such a semiconductor device, the collector electrode 2 is put at a positive potential relative to the emitter electrode 3, and the first and second insulated gate electrodes 4, 6 are put at potential positive relative to the emitter electrode 3. Under this condition, the surfaces of the p-type layers 113 contiguous to the insulating film 5 is inverted into n-type, and electrons flow through the emitter electrode 3 to the n.sup.+ layers, the n-type inverted layers, and the n.sup.- layer 12, and into the p.sup.+ substrate region 11. As a result, the injection of holes .sym. having positive charges from the p.sup.+ substrate region is promoted, and the holes flow through the n.sup.- layer 12 and the p-type layers 113 into the emitter electrode 3. By the flows of the electrons and holes, an electric current flows from the collector 2 into the emitter electrode 3. To switch the semiconductor device from the ON state to the OFF state, it is only necessary to remove the potentials from the first and second insulated gate electrodes 4, 6. Then, the n-type inverted layer will disappear, and the electron current is cut off, with the result that the injection of holes stops and the current stops flowing.
For the IGBT, the substrate region 11 is of p.sup.+ type, and therefore, an IGBT is formed in a four-layer structure comprising a p.sup.+ substrate 11, n.sup.- layer 12, p-type layer 113, and n.sup.+ layer 114. Therefore, the IGBT has a parasitic thyristor formed therein. Once the parasitic thyristor has started to operate, it becomes impossible to control their operation with the first and second insulated gates 4, 6, leaving the current to multiply, resulting in the device being destroyed by Joule heat. This is referred to as a latchup. This latchup can occur not only in the region A but also in the region B. In some device structures, the region B is more susceptible to a latchup, and the breakdown strength of the IGBT is determined by the region B. FIG. 6 shows a device structure in which preventive measures have been employed. Specifically, by having the p-type layer 113 and the p.sup.+ layer 115 contiguous to each other, the electron current is prevented from flowing through the n.sup.+ layer 114 located in the region B. In other words, the peripheral p.sup.+ layer 115 is given a higher carrier concentration than the p-type layer 113 so that the peripheral p.sup.+ layer 115 is less liable to be inverted to n-type under the second insulating gate 6. At the same time, the insulating film 7 is made thick. In consequence, the quantity of holes .sym. present in the region B is made smaller than in the region A, and a voltage drop in the p-type layer 113 and the peripheral p.sup.+ layer 115 which is caused by the resistance Rp below the n.sup.+ layer 114 and the hole current is made lower than the diffusion potential (about 0.7 V at room temperature) of the p-type layer 113, the peripheral p.sup.+ layer 115, and the n.sup.+ layer 114, making it impossible for a latchup to occur in the ordinary ON state. In addition, since the peripheral p.sup.+ layer 115 is short-circuited to the emitter electrode 3 at the boundary between the regions A and B, a small amount of holes is collected quickly in turning off the device, thus reducing the turn-off time.
On the other hand, a device of this structure in which the substrate region 11 is an n.sup.+ layer is a power MOSFET. To turn on the power MOSFET, like in the IGBT, while the collector electrode (drain electrode) 2 is placed at a positive potential, a positive potential is applied to the first and second insulated gate electrodes 4, 6. Thus, an inverted layer is produced in that part of the p-type layer just below the surface of the insulating layer 5, electrons flow through the n.sup.+ layers 114, the inverted layers, the n.sup.- layer 12 to the n.sup.+ substrate region 11, and as a result, an electric current flows from the drain electrode 2 to the emitter electrode (source electrode) 3. To turn off this power MOSFET, it is only necessary to remove the potential from the insulated gate electrodes. Then, the inverted layers disappear, so that the current is cut off. In the meantime, the power MOSFET includes p-n diodes each comprising an n.sup.+ substrate region 11, an n.sup.- layer 12, and a p-type layer 113 (peripheral p.sup.+ layer 115). Some attempts have been made in the application of this p-n diode as a feedback diode. For example, when a potential is applied to the source electrode 3 of the power MOSFET, which is positive with regard to the drain electrode 2, a current is supplied in the forward direction by using this diode. In this process, holes .sym. are injected into the n.sup.- layer 12 from the p-type layer 113 and the p.sup.+ layer 115. Next, the moment the source electrode becomes negative with respect to the potential at the drain electrode 2, the holes .sym. are attracted to the source electrode 3. In this case, if the peripheral p.sup.+ layer 115 is short-circuited to the source electrode 3 in the vicinity of the peripheral p.sup.+ layer 115, the peripheral p.sup.+ layer to serve as a resistance when the holes are attracted to the source electrode 3 is reduced in length, permitting the diode to recover at high speed. At this time, the current of holes .sym. flow through the p-type layer 113 (peripheral p.sup.+ layer 115) beneath the n.sup.+ layer 114 located closest to the peripheral region B.
In the device of FIG. 6, the IGBT or the power MOSFET is not so constructed as to securely prevent the parasitic thyristor or the parasitic transistor from operating when the device is switched from the ON state to the OFF state at high speed, and therefore is liable to be destroyed. More specifically, the p-n junction is forward-biased by the resistance Rp of the p-type layer 113 (peripheral p.sup.+ layer 115) beneath the n.sup.+ layer 114 closest to the peripheral region B, and by the current of injected holes .sym. and the discharge current of the p-n junction. As a result, the parasitic thyristor (parasitic transistor) comprising the p.sup.+ substrate (n.sup.+ substrate) 11, the n.sup.- layer 12, the p-type layer 113, and the n.sup.+ layer 114 is put into operation, which has been a problem.
Furthermore, in the device of FIG. 6, the p-type layers formed in the n.sup.- layer 12 on both the regions A and B have the same depth. Therefore, due to a transient voltage which occurs in the transient state causing avalanching to take place in the whole area including the region A), and the device becomes uncontrollable by the operation of the parasitic thyristor (parasitic transistor).
The present invention has been made with a view to providing an IGBT or a power MOSFET constructed such that a parasitic thyristor or a parasitic transistor does not operate while the switching function, particularly the high-speed turn-off function, is maintained.